The STACEE detector is based on the heliostats of the National Thermal Solar Test Facility (NSTTF) located at Sandia National Laboratories in Albuquerque, New Mexico. Forty-eight of the 212 heliostats in the array are used to reflect Cherenkov light, produced by gamma-ray induced air showers, onto three identical telescopes located atop a central tower. The telescopes each comprise a 1.9 m diameter secondary mirror and 16 photomultiplier tubes (PMTs). The arrival of a cosmic gamma ray gives rise to simultaneous pulses in a subset of the PMTs and this condition is used as a criterion for triggering the readout of STACEE. Night sky background and other random noise will not produce coincident signals in different channels and can therefore be rejected.
This simple picture neglects the fact that with enough random noise and with loose enough coincidence criteria, background can fake the interesting physics. To eliminate background one can decrease the time window which defines the coincidence and/or one can require more channels to fire. Also, one can increase the threshold for a given channel to fire. The last two of these three techniques work against one of the prime physics motivations of STACEE, namely to lower the energy threshold for the detection and measurement of gamma rays. It is our aim to exploit the first technique to the maximum dictated by the basic physics of the air shower process. This means requiring the signals from different elements of the detector to overlap at the level of 10 ns. This limit is set by the arrival time fluctuations of Cherenkov photons which are in turn defined by the showering process.
Achieving coincidences at a level of less than 10 ns is common in particle physics experiments and most of the electronics used in STACEE are capable of this task. The difficulty here is that the geometry of the problem changes continuously as the source, which is being tracked by the detector, appears to move across the sky due to the rotation of the earth. The gamma-induced air shower produces a burst of Cherenkov photons which arrive at the heliostat field as a plane, oriented such that the normal is in the direction of the shower axis. Thus each heliostat is hit at a different time depending on the angle of the shower. Light from the heliostats then proceeds to the secondary mirrors and phototubes. The times at which the phototubes fire relative to one another change throughout the night and these changes must be corrected for in order to preserve the tight time coincidences.
The scale of the changes are related to the geometry of the STACEE detector. The spacing between heliostats can be of the order of 100 m and the angles of the incoming showers can vary between +-45 degrees. Thus the firing times for the phototubes can be dispersed by the order of several hundred nanoseconds. To keep simultaneity at the level of a few nanoseconds requires a dynamic delay which has a step size of 2-3 ns and a range of more than 100 ns. The exact value of the upper limit depends on the angular acceptance desired (how far down from the zenith one wants to track sources) and the particular triggering strategy adopted. For example, one can group several neighbouring channels into a cluster to form a pre-trigger and then require several pre-triggers in the final trigger. This reduces the geometry problems somewhat.
The final issue to be considered in a dynamic delay scheme is the deadtime. There are commercial systems available to accomplish what we need in STACEE. Indeed we are using them at the moment. However they are subject to deadtime; a pulse in the delay system cannot be followed immediately by another. This means that the primary rate of digital pulses being sent to the pipeline must be lower than a given amount. To keep this rate low requires a higher threshold on the analog pulses coming from the PMT and this raises the effective energy threshold of the experiment.
There is nothing on the market which adequately fulfills our needs so we have adopted a custom made solution based on an idea of one of us. This is to use a series of flip-flop circuits (a shift register) as a digital pipeline. The basic concept is to feed the shift register serial input with a digital signal made from discriminating the phototube pulse. This digital pulse propagates through the shift register at a rate given by the clocking speed of the system. It can be followed at any distance by another pulse so its deadtime is limited to the width of a single clock pulse. The pattern of active bits in the shift register at any given moment constitutes a data word.
The shift register supplying the delay is actually implemented in a series of shift registers of sizes 1, 2, 4, 8, etc.. Between each shift register is a 2-to-1 multiplexer. Each multiplexer either routes the pulse through, or around the shift register in front of it. In this way, the desired delay can be set by controlling the multiplexers (switches). Each bit in the delay time controls the flow through a shift register, such that the lower order bit controls the shift register of size 1, the second order bit controls the shift register of size 2, etc.. The total delay is thus given by a register which holds the delay time.
This is a `brute force' solution which relies on the economies inherent in digital electronics but since we only require 48 channels, a special chip (ASIC) will not be economically viable. This means that we will have to construct the device from standard components. As a design specification we have chosen a step size of 3 ns and a range of 1 microsecond. This implies a clock speed of 333 MHz and a shift register that is a maximum of 333 units long. Such high speed electronics is usually built with ECL technology which is expensive and power hungry. We have decided to avoid these two negative features by using the following trick.
We divide the clock by eight and make eight copies of this slower clock. Each of the 42 MHz clocks is phase delayed by 3 ns with respect to each other. The input signal is presented to eight latches. Each latch is clocked by a different 42 MHz clock phase. One, and only one, of the clock edges will coincide in time with the input signal and thus capture it in a latch for subsequent delay in a pipeline. Each digital pipeline is as described above but the clock speed is eight times slower and the number of delay units is eight times fewer. The overall number of flip-flops remains the same but the slower speed allows us to use fast TTL (Texas Instruments' F logic SN54/74F) which is cheaper and consumes less power. The slower speeds also make board layout less problematic. To recover the 3 ns resolution, the 3 lowest order bits in the delay time are used to select the correct channel of the eight that will be used in subsequent logic as the delayed digital pulse of the PMT.
Douglas M. Gingrich
(gingrich@phys.ualberta.ca)